Wave-edge comparator



Oct. 21, 1969 Filed March 21, 1967 C. E. LENZ 5 Sheets-Sheet 1 C C2 2 i'w HRST STEP 50 INPUT DETECTOR SIGNAL X0 4 xelm\ ERROR x (t) ENABUNG cSIGNALS DETECTOR J gBSC$ATOR xeZmJ SIGNAL c P531 D og ToR i2 sqeNAL x u)x m J TWO-PHASE 3 CLOCK FIGJ NORMALIZED ERROR x I NVEN TOR.

CHARLES E. LENZ ATTO RN EY Oct. 21,

CLOCK SIGNALS COMPARATOR INPUTS STEP DETECTOR "2" STEP DETECTORPOSITIVE- TOLERANCE COUNTER NEGATIVE- TOLERANCE COUNTER COMPARATOROUTPUT E. LENZ 3 Sheets-Sheet TIME SCALE DISCONTINUITY 15ml m 2s '5! s2ae'--} 2% I c n) mil Kl v.4 lrlsl l I I.) HI I I I Hmkusmou mks; l ()2-I II I I x: iu 172*? Q H'bTI I i I '2 x m I as. as

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ATTORNEY CHARLES E. LENZ United States Patent Office 3,474,414 PatentedOct. 21, 1969 US. Cl. 340-146.1 Claims ABSTRACT OF THE DISCLOSURE Asystem for generating an output if a first signal occurs within aninterval starting a specified time before and ending a specified timeafter a second signal. The first and second signals are applied to apair of step detectors, each of which is operative to generate a pulseupon the occurrence of a specified transition of its input signal. Thepulses from the step detectors are applied to an error detector whichgenerates an output pulse if the time displacement between two adjacentinput pulses satisfies the condition specified above.

BACKROUND OF THE INVENTION Field of the invention The present inventionrelates to a wave-edge comparator and, more particularly, to a systemfor generating an output signal which indicates whether the displacementbetween specified transition times of two input signals lies withinprescribed bilateral tolerances.

Description of the prior art In numerous types of prior-art electronicsystems, it is necessary to know the time of occurrence of a specifiedevent. Furthermore, in such prior-art systems, it is often necessary toknow whether a first specified event occurs within an interval startinga predetermined time before and ending a predetermined time after asecond specified event. It therefore becomes necessary to provide asystem for generating a time-varying output signal which will indicatewhether the time displacement between specified events lies withinprescribed bilateral tolerances. In addition, for a fully versatilesystem, the absolute values of the bilateral tolerances should not haveto be equal.

Several prior-art systems have been proposed to meet these requirements,but none has been fully successful. Each specified event is generallyconverted into an electrical signal, a predetermined characteristic ofwhich changes its value upon the occurrence of the event. Theseelectrical signals then provide the inputs to the comparator. In many ofthese prior-art systems, it is necessary for at least one of the inputsignals to be fully synchronized with a timing means. This requirementhas an obvious disadvantage where it is necessary to compare tworandomly occurring signals. In still other priorart systems, the rangeof values of the time displacement between the two input signals whichwill cause a signal to appear at the comparator output is established interms of unilateral tolerances. In other Words, a first signal mustoccur within an interval of predetermined length which either starts orends with occurrence of a second signal in order to generate an outputsignal. Such operation is unsatisfactory in most applications because itis usually necessary to construct a system which will generate an outputif the first signal occurs within an interval starting a specified timebefore the second signal in order to establish the positive toleranceand ending a specified time after the second signal in order toestablish the negative tolerance. In addition, a truly versatilecomparator permits variation of the positive and negative toleranceswithout basic design modification, an objective which has not beenattained heretofore. Finally, the known devices are usually complex,requiring time-consuming interpretations of each measurement, andrequire frequent calibration to avoid deterioration of the accuracy ofthe system.

SUMMARY OF THE INVENTION It is the purpose of the present invention toprovide a system which eliminates all of the fundamental limitations ofprior-art systems. According to the present invention, each specifiedevent is first converted into a logical signal, i.e., upon occurrence ofthe specified event, the signal level goes through a transition from thelogical value of 0 to the logical value of 1. These logical signalsprovide the inputs to the wave-edge comparator which is operative togenerate a logical, time-varying output signal that indicates, with aknown degree of certainty, whether or not the displacement between thespecified transition times of the two logical signals lies withinprescribed bilateral tolerances. Such a device is useful for comparing,on a go or no-go basis, any two quantities which can be transformed intotime displacements. Typical applications for such a device includeautomatic built-in test equipment for avionic systems and test elementsfor automatic machine tools. With the system of the present invention,the range of values of the time displacement which will cause a signalto appear at the comparator output is established in terms of quantizedbilateral tolerances. The ability to program the comparator in a mannerwhich conforms to standard engineering practice in specifying tolerancesresults. An attendant advantage is the elimination of unnecessarycomputation in programming the comparator to meet given specifications.An additional advantage of the present system is that the range of thepermissible value of the time error is expressed in terms of bilateraltolerances which can be unequal. Increased versatility of the comparatorresults, and the computation necessary in programming the comparator toconform to specifications is thereby still further reduced. Anotherfeature of the present invention is that the comparator can accommodatetwo arbitrary input signals without requiring either signal to besynchronized. Full compatibility with input signals which representanalog quantities as continuously variable time displacement results. Anassociated advantage is the ability to provide from such input signals acomparator output signal which can be utilized directly by an on-linedigital computer.

The comparator of the present invention is fully synchronized so thatits output signal rises and falls at times which are accuratelycontrolled by a clock signal. This feature also contributes to fullcompatibility with on-line digital computational equipment. Anadditional advantage is the elimination of equipment to synchronizeoperation of the wave-edge comparator with that of an associated digitalcomputer. The versatile nature of the present comparator permitsconvenient variation of tolerances without basic design modifications. Acomparator applicable to a variety of requirements, in rapid sequence ifnecessary, results. An attendant advantage is the ability to meet manyrequirements with a single product design, or even with a singlecomparator by means of switching. Tolerances may be varied automaticallyor remotely where required.

The present comparator provides a go or no-go indication rapidly.Elimination of complex and time-consuming interpretation of eachmeasurement results. Corresponding advantages are the elimination ofunnecessary associated logical decision-making devices and theminimization of the effects of time variation of the error while ameasurement is being made.

The accuracy and resolution of the present comparator are established bya highly stable crystal clock, thereby eliminating frequent comparatorcalibration. Continuing repeatability of measurements results. Anassociated advantage is the small amount of maintenance required by thistype of comparator.

The present comparator performs all required functions by utilizingcomponents having only two states. A fully digital comparator resultswhich provides the advantage of stability in the presence ofenvironmental variations, voltage changes, and aging to a greater extentthan that attainable with an analog device. In addition, the comparatorutilizes no monostable elements, thereby providing greater noiseimmunity than would otherwise be possible. A corresponding advantage isan increase in the reliability of the output signal generated.

In accordance with this invention, there is provided a comparator whosebasic inputs are a first input signal and a second input signal withwhich it is to be compared. In addition, an arbitrary number of enablingsignals can be accommodated. All such enabling signals must be presentsimultaneously to permit operation of the comparator. The comparator hasa single output signal in the form of a pulse. This output pulse appearswhen, and only when, a -to-1 transition of the first input signal occursno earlier than a specified time before and no later than a specifiedtime after a 0-to-1 transition of the second input signal. The length ofthe output pulse, when present, depends upon the relative times ofadjacent 0-to-1 transitions of the two input signals.

The basic components of the wave-edge comparator are a two-phase clock,two identical step detectors, and an error detector. The two-phase clockreceives no input signals, but generates periodic primary and secondaryclock signals for synchronizing operation of all other basic components.Both clock signals are identical except for time displacement Each ofthe identical step detectors utilizes the clock signals forsynchronization. In addition, each accepts a different one of the inputsignals to be compared. Each step detector generates a pulse shortlyafter each O-to-l transition of its input signal. The error detectorutilizes the clock signals for synchronization and will operate onlywhen the enabling signals simultaneously have the logical value 1. Theerror detector also receives the output signals furnished by the stepdetectors and is operative to provide an output pulse if thedisplacement between two adjacent pulses from the step detectors fallswithin predetermined tolerances.

It is, therefore, an object of the present invention to provide awave-edge comparator which is operative to generate an output signalwhen the displacement between specified transition times of two inputsignals lies within prescribed bilateral tolerances.

It is a further object of the present invention to provide a wave-edgecomparator wherein the range of values of the time displacement whichwill cause an output is established in terms of quantized bilateraltolerances.

It is a still further object of the present invention to provide awave-edge comparator in which the range of permissible values of thetime displacement is expressed in terms of bilateral tolerances whichcan be unequal.

It is another object of the present invention to provide a wave-edgecomparator which will accommodate two arbitrary input signals withoutrequiring either signal to be synchronized.

It is still another object of the present invention to provide a fullysynchronized comparator output signal which rises and falls at timesthat are accurately controlled by a clock signal.

Another object of the present invention is to provide a wave-edgecomparator which permits convenient variation of tolerances Withoutbasic design modification.

Still another object of the present invention is to provide a wave-edgecomparator which generates a go or nogo indication rapidly.

Still other objects, features, and attendant advantages of the presentinvention will become apparent to those skilled in the art from areading of the following detailed description of the preferredembodiment constructed in'accordance therewith, taken in conjunctionwith the accompanying drawings wherein:

BRIEF DESCRIPTION OF THE DRAWING FIGURE 1 is a block diagram showing thebasic components of the wave-edge comparator of the present invention;

FIGURE 2 is a graph showing the probability of an output signal beinggenerated when both input signals areasynchronous and statisticallyindependent of the clock signals;

FIGURE 3 is a more detailed diagram of the components of the presentinvention; and

FIGURE 4 shows a series of logical waveforms useful in explaining theoperation of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to the drawingsand, more particularly, to FIGURE 1 thereof, there is shown a blockdiagram of the wave-edge comparator. The comparator will be discussed interms of the required inputs, the output generated, and the functions ofthe basic components. All transmission of information to and from thecomparator and between components is by means of two-level logicalelectrical signals, one such level being assigned the logical value 1and the other level being assigned the logical value 0. In addition,each signal input and output is normally false,v i.e., normally has thelogical value 0.

As shown in FIGURE 1, the basic components of the wave-edge comparatorare a two-phase clock 1, identical step detectors 2 and 3, and an errordetector 4. Two-phase clock .1 receives no input signals but isoperative to generate periodic primary and secondary clock signals C (t)and C 0), respectively, each a function of time t and having a period1', for synchronizing operation of all other basic components. All timeswill be expressed in seconds. Both clock signals are identical exceptfor time displacement, i.e.,

Each clock signal is normally false. The clock pulse length, 'rtypically lies within the interval During each such interval, a clockpulse remains continuously true, i.e., has the logical value 1. When 10, the initial C (t) pulse is last true at t=-r.

The basic inputs to the compartor are the first input signal X,,( t) andthe second input signal X t) with which X,,(t) is to be compared. Thecomparator is designed to accommodate only basic input signals for whichadjacent transitions of the same signal are separated by no less than'r+'r where 1-,, is the enabling time of the type of flip-flop employedin step detectors 2 and 3 and error detector 4. Normally, however, suchtransitions will be separated by a considerably larger interval thanthis minimum. For present purposes, at least the O-to-l transitions of X(t) will be assumed to be initiated by l-to-O transitions of the clocksignal (2 (1).

In addition to the basic inputs to the comparator, an arbitrary number1; of enabling signals can be accommodated. All such enabling signalsmust be true simultaneously to permit operation of the comparator. Thus,to enable the comparator, the logical relation X,,, i 1 1 U 1 must besatisfied. In the particular case to be described below where 1 :2,Relation (3) reduces to The comparator has the single output X (t). Atrue pulse appears at X (t) when, and only when, a O-to-l transition ofX,(r) occurs no earlier than (p /z)r before and no later than (q /2)Tafter a -to-1 transition of X (t), where the positive integers p and qare design parameters of the comparator. Thus, if a 0-to-1 transition ofX,,(t) occurs at time t,,,+ for each positive value of the integer i anda 0-to-1 transition of X (t) occurs at time t for each positive value ofthe integer k, then an X (t) pulse will occur only for those sets ofpermissible values of i and k for which (P e bk al q) "'""e where e isthe time-difference error between specific O-to-l transitions of X,,(t)and X (t). To represent equal bilateral tolerances or for other reasons,appropriate parameter choice can make the effect of 'r negligible inRelation 5 The length of an output pulse, When present, depends upon therelative times of adjacent O-to-l transitions of X,,(t) and X (t). An X(t) pulse can have any length /2)1-+1- for which the integer j satisfiesthe relation where {p, pq 41. K1

Step detectors 2 and 3 are identical. Each has as inputs the clocksignals C (t) and C (t) for synchronization. In addition, each stepdetector accepts one of the input signals to be compared, step detector2 accepting X,,(t) and step detector 3 accepting X (t). Step detectors 2and 3 generate the normally false output signals X ,,(t) and X (t),respectively. The signal V,,(t) goes true for a period 1-/2 soon aftereach O-to-l transition of X (t). Similarly, the signal X (t) goes truefor a period 1/2 shortly after each O-to-l transition of X-,,(t). IfX,,(t) goes true at time t where i is a positive integer, then X,,,(t)will go true at time t in response to the next C (t) trailing edge atleast 'T later. It follows that In Relations (8) and (9), the positiveintegers m and n are chosen to satisfy the inequalities shown, and 6 isa vanishingly small positive quantity representing the response time ofthe logic elements involved.

Error detector 4 also utilizes the clock signals Q0) and 0 0) forsynchronization. Error detector 4 will operate only when the enablingsignals X (t) and X (t) are simultaneously true. The basic inputs oferror detector 4 are the signals X ,,(t) and X -,,(t) furnished by stepdetectors 2 and 3. Error detector 4 has the single normally false outputsignal X (t), which constitutes the only output of the wave-edgecomparator.

The basic purpose of error detector 4 is to provide a true output pulseat X (t) if the displacement between adjacent X (t) and X (t) pulses iswithin predetermined tolerances. Let the ith X (t) pulse when t 0 have al-to-O transition at time where n is a positive integer. An X (t) pulsewill result from the ith X (t) pulse and the kth X (t) pulse if, andonly if,

PT sbk sai q If Relation (12) is satisfied, an output pulse from theerror detector will occur. The output X (t) will remain true for theinterval and where Although use of the comparator has been discussed indetail only for the case where X,(t) alone is asynchronous and at leastthe O-to-l transitions of X (t) are synchronized by l-to-O transitionsof C (t), the comparator can also be utilized effectively when both X,,(t) and X (t) are asynchronous and statistically independent of theclock signals. In the case of such fully asynchronous inputs, however,the presence or absence of an X,,(t) pulse no longer indicatesconclusively that a measured error e is either within or outside of anysingle interval such as that shown in Relation(5). Rather, thecomparator output must be interpreted on a statistical basis. Toillustrate, if a given measurement is of an error having the normalizedvalue -r (16) a function G(x) can represent the probability that themeasurement will initiate an X (t) pulse. The probability G(x) equals 1only in the interval and decreases linearly to remain 0 throughout theintervals x-q and xgp. Consequently, it is not possible to predict withcomplete certainty whether or not measurement of a normalized error ineither of the intervals will initiate an X (t) pulse. A typical G(x)function is plotted in FIGURE 2.

To interpret the comparator output effectively, a statistical hypothesiscan be formulated utilizing decision points located at x and x Underthis measurement hypothesis, for a given measurement it will be assumedboth that an X (t) pulse indicates that e/qlies within the confidenceinterval E 1 7: 2 and that absence of an X,,(t) pulse indicates thateither S 1 19 or No values of x and x exist which permit use of themeasurement hypothesis with complete certainty. For example, if

contrary to the hypothesis, an X,,(t) pulse can be initiated even by ameasured error outside of the confidence interval defined by Relation(18) when the normalized error is within either of the intervalsConsequently, to determine the reliability of the measurement hypothesiswith given values of x and x it is useful to evaluate two confidencecoefiicients. The first confidence coefficient equals the probabilitythat a given X (t) pulse has been initiated by a normalized measurederror within the confidence interval defined by Relation (18). Thesecond confidence coefiicient is the probability that, for a givenmeasurement, the normalized error is outside of the confidence intervalif not X (t) pulse is initiated.

To evaluate the confidence coefficients, for a given measurement let Abe the event that the normalized error lies within the confidenceinterval defined by Relation (18), B be the event that an X (t) pulse isinitiated, and C be the event that where dx is infinitessimal.Evaluation of the first confidence coefficient, C requires determinationof the necessary conditional probability in accordance with the equationP AB The conditional probability P(B/C) approaches G(x) as dx approaches0. Consequently, it can be written that P(BC) P(BC) P(C) f(a:)dx (25)where f(x) is the probability density function of the normalized errorand will be assumed to be continuous. The last expression in Relation(25) follows from observation that P(C)=f(x)dx (26) A typical continuousprobability density function, f(x), is also plotted in FIGURE 2.

Relation (25) can be solved for the probability that events B and C bothresult from a given measurement to yield while choice of an infiniteinterval leads to the probability Substituting Relations (28) and (29)into Relation (24) yields the required relation tor the first confidencecoefficient.

The second confidence coefficient, Cg, can be defined in a similarmanner. This confidence coefficient is given by the equation The sameset of decision points x and x cannot normally maximize both theconfidence coefiicients C and C and Cg C Clearly C is 1 if the relationt q P 2 is satisfied. However, C decreases from 1 if x is decreased or xis increased in violation of the relation in order to conform withRelation (32).

Despite the incompatibility of Relations (32) and (33), values can beassigned to x and x which optimize both C and Cg under given conditions.To determine these optimum values of at; and x let G and L be the gainand the absolute value of the loss, respectively, if the measurementhypothesis associated with Relations (19) through (21) is valid orinvalid when an X (t) pulse is initiated, let G; and Lg apply when ameasurement does not initiate an X (t) pulse. The quantities G G5, L andL5 are functions of x and x A figure of merit for the measurementhypothesis can now be defined as Theory of Signal Detection, London,Pergamon Press, 1960).

A typical choice of decision points is 1=q and With these decisionpoints, every measurement which initiates an X,,(t) pulse will be of anormalized error within the confidence interval Consequently, theconfidance coefficient C is 1. The

value of the confidence coefficient C however, depends upon the extentto which the chosen values of p and q satisfy the relation P(A/B)1P(A/B) (38) Operation of the comparator components shown in FIGURE 1will now be described in detail with reference to FIGURE 3, which showsthe logic diagram of the wave-edge comparator, and to FIGURE 4, whichshows waveforms useful in explaining the operation of FIGURE 3. InFIGURE 4, time t is the abscissa of every curve. The upper value of eachcurve is logical 1, and the lower value is logical 0.

All logical elements used in the comparator communicate by means ofvoltages which can assume steady-state values only in either of twomutually exclusive intervals. When in one arbitrarily selected interval,a voltage is said to be in the true state and to represent the logicalvalue 1. When in the other interval, a voltage is said to be in thefalse state and to represent the logical value 0.

All flip-flops are of the JK type (ref.: Montgomery Phister, Jr.,Logical Design of Digital Computers, New York, John Wiley & Sons, Inc.,1959, pp. 128-129, 134- 135). Such a flip-flop is exemplified byflip-flop 201 in FIGURE 3. A flip-flop can assume either of two logicalstates. In the true (1) state, the 1 (normal) and (complement) outputterminals generate signals having the logical values 1 and 0,respectively. In the false (0) state, the l and 0 output terminalsgenerate signals having the logical values 0 and 1, respectively.

Each flip-flop has an override-set input and an overridereset input,such as those shown entering the top and bottom, respectively, offlip-flop 201 in FIGURE 3. The override inputs do not affect theoperation of a flip-flop when each such input has the logical value 0.System design must prevent both override inputs of a flip-flop fromsimultaneously assuming the logical value 1, because the response of theflip-flop to this condition cannot be predicted. When the logical valueof either override input changes to l, a flip-flop responds immediately,regardless of the states of all other inputs. A flip-flop remains in orassumes the true state in response to a 1 signal at the override-setinput and remains in or assumes the false state in response to a 1signal at the override-reset input.

When both override inputs are simultaneously 0, a flipfiop operates in amode in which it is responsive to inputs at the J, K, and T terminals.In this mode, a flip-flop can change state only in response to a l-to-Otransition of an input at the T (trigger) terminal. For the flip-flop toactually change state at such a time, however, appropiate logical valuesmust have been applied to the J and K terminals continuously during thepreceding period of length no less than T where 'r., is the enablingtime of the flip-flop. During this period, any one of four possible setsof logical values can be applied to the I and K terminals of theflip-flop. If a logical 0 is applied to both terminals, the flip-flopwill not change state. If a logical 1 is applied to both terminals, theflip-flop will always change state. If a logical 1 and 0 are applied tothe I and K terminals, respectively, the flip-flop will change to orremain in the true state. If a logical 0 and 1, respectively, areapplied to the I and K terminals, the flip-flop will change to or remainin the false state.

All gates shown in FIGURE 3 are AND gates of the type described in theliterature (Montgomery Phister, Ir., Logical Design of DigitalComputers, supra, pp. 22-24, 32-33). Such a logical element is typifiedby gate 204 in FIGURE 3. A gate of this type produces a true output if,and only if, all inputs are simultaneously true.

The logical inverters employed are typified by inverter 202 in FIGURE 3.Such an element produces an output which is the logical complement ofits input.

Response delay is an important characteristic of any logical element. Tocomprehend the following discussion of the wave-edge comparator,however, it is suflicient to recognize that a flip-flop requires a shorttime to respond to each l-to-O transition at its T terminal and,therefore, changes state only after the trigger signal initiating thechange is false.

Two-phase clock 1 provides the synchronizing signals for the wave-edgecomparator. Reference will be made to the significant characteristics ofthe output signals of twophase clock 1, rather than to the internaloperation of the clock, since a comprehensive discussion of the internaloperation is described in my copending application Ser. No. 394,977,filed Sept. 8, 1964, and entitled Digital Reference Source.

The logical outputs C (t) and C (t) of two-phase clock 1, each a pulsetrain of period '1', are shown as curves and 11 in FIGURE 4. The firstpulse of Q0) shown is last true at time '1', the first pulse of C 0) attime 7/2. Idealized pulses of length T approaching 0 are shown in bothtrains. Instantaneous logical values of discrete binary 10 signals areplotted in FIGURE 4, rather than the voltage levels to which theselogical values correspond. The mathematical relationship between C (t)and C 0) is given by Relation 1).

The logic diagrams of step detectors 2 and 3 appear in FIGURE 3. Sinceboth step detectors are identical, explanation of the operation of onewill suffice to explain the operation of both.

Step detector 2 consists basically of two flip-flops, 201 and 203. Thefirst input signal, X,,, (t'), is applied to the J input terminal offlip-flop 201. Input signal X (t) is also applied to inverter 202, andthe resultant complement f lt) is applied to the K input terminal offlip-flop 201. Clock signal C (t) is applied to the T input terminal offlip-flop 201. Upon termination of the first C (t) pulse ending at least'r after X,,(t) changes state, flip-flop 201 assumes the same logicalstate as X (t) and remains in this state until after X,,(t) againchanges state. The 1 output terminal of flip-flop 201 is connected tothe J input terminal of flip-flop 203 and to a first input of AND gate204. The 0 output terminal of flip-flop 201 is connected to the K inputterminal of flip-flop 203. clock signal C (t) is applied to the T inputterminal of flipfiop 203. The 0 output terminal of flip-flop 203 isconnected to the second input of AND gate 204. The output of stepdetector 2, X ,,(t), is derived from AND gate 204. The state offlip-flop 203 at time t is always the same as that of flip-flop 201 attime Therefore, in each interval of duration 'r/Z following a 0-to-1transition of flip-flop 201, true signals exist at the 1 output terminalof flip-flop 201 and at the 0 output terminal of flip-flop 203. Wheneverthis condition occurs, a true pulse is emitted at the output X (t) byAND gate 204. At all other times, X ,,(t) is false.

The operation of step detector 3 is the same as that just described forstep detector 2 and can be derived from said description by substitutingX (t) for X (t), by substituting X (t) for X (t), and by adding to thenumber designating each inverter, flip-flop, and AND gate to whichreference was made in discussing step detector 2.

Waveforms relating to step detectors 2 and 3 when t 0 appear in FIGURE4. The respective inputs X,,(t) and X (t) of step detectors 2 and 3,which are also the inputs of the wave-edge comparator, are shown aswaveforms 12 and 13. In the following discussion, the case will beconsidered where X,,(t) and X (t) are both asynchronous, although eitheror both of these signals can be synchronized with the trailing edges ofpulses of either C (t) or C (t). Furthermore, it should be noted thatbecause of synchronization by step detectors 2 and 3, any transition ofX,,(t) or X (t), such as transition 25 of X (t), could also haveoccurred at any time later than the last, but no later than the next orcurrent, instant T before a 1-to-0 transition of C 0) without modifyingthe response of the comparator.

The outputs of flip-flops 201 and 203 in step detector 2 appear aswaveforms 14 and 15, while the output of step detector 2 is shown aswaveform 16. After X,,(t) goes true at 25, flip-flop 201 responds to thetrailing edge of the next C (t) pulse, at 26, by also going true at 27.The trailing edge of the succeeding C (t) pulse, at 28, then causesflip-flop 203 to also assume the true state at 29'. In the periodbetween 27 and 29, a true pulse 30 appears at X (t). Similarly, 0-to-1transitions of X (t) at 31 and 32 cause X (t) pulses to be generated at33 and 34, respectively.

Neither step detector is responsive at its output to l-to-O transitions.of its input signal. For example, immediately after the l-to-Otransition of X,,(t) at 35, the fiip-fi0ps 201 and 203 in step detector2 respond to the trailing edges of the following C (t) and C (t) pulses,at 36 and 37, by

going successively false at 38 and 39. Nevertheless, X does not respondat 40.

The output of step detector 3 is shown as waveform 17 in FIGURE 4. Inresponse to the O-to-l transitions of the comparator input X (t) at 41,42, and 43, flip-flops 30 i and 303 cause AND gate 304 to emit true X(t) pulses at 44, 45, and 46, respectively.

The logic diagram of error detector 4 is also shown in FIGURE 3. Errordetector 4 consists of a positive-tolerance counter 5, anegative-tolerance counter 6, and a pass gate 7. Tolerance counters 5and 6 are similar. Both counters count C (t) pulses and can be reset to0. Positive-tolerance counter 5 establishes the parameter p by beingpreset to stop counting C (t) pulses when the count C (t) which itcontains equals the value of 12. Likewise, negative-tolerance counter 6establishes the parameter q by being preset to stop counting C (t)pulses when the count C U) which it contains equals the value of q.Although tolerance counters 5 and 6 need not have identical capacitiesnor be of any specific type, both units shown in FIGURE 3 arethree-stage binary counters capable of counting from 0 (binary 000) to 7(binary 111) when appropriately preset.

Because of the similarity of tolerance counters 5 and 6, onlypositive-tolerance counter 5 will be described in detail. Any positivenumber of binary stages v can be employed, subject toresponse-propagation considerations, in order to obtain apositive-tolerance counter having the capacity However, the case wherev=3 will be described specifically.

Positive-tolerance counter 5 is basically a three-stage binary ripplecounter consisting of flip-flops 501, 502, and 503 with associated resetand preset logic. The T input terminal of flip-flop 501, thelowest-order flip-flop, is connected to the clock signal C (t).Consequently, whenever a signal having the logical value 1 is appliedsimultaneously to its 1 and K input terminals, flip-flop 501 changesstate in response to every l-to-O transition of C (t). Both the J and Kinput terminals of flip-flops 502 and 503 are connected to a fixedvoltage of logical value 1, and the T input terminal of each of theseflip-flops is connected to the 1 output terminal of the flip-flop of thenext lowest order. More particularly, the T input terminal of flip-flop502 is connected to the 1 output terminal of flip-flop 501, and the Tinput terminal of flip-flop 503 is connected to the 1 output terminal offlip-flop 502. Consequently, the state of each of these higher-orderflip-flops changes when the state of the preceding counter stage goesfrom 1 to 0. When enabled, positive-tolerance counter 5 thus counts thetrailing edges of C (t) pulses applied to the T input terminal offlip-flop 501 to provide an instantaneous positive-tolerance count InRelation (40), F (t) represents the instantaneous logical state (0 or 1)of flip-flop 501+i.

Appropriate reset logic starts the counter with the count C (t)=0. Thisis accomplished by applying X U) from step detector 2 to a reset ANDgate 504 together with the clock signal C (t). The output of reset ANDgate 504 is applied to the override-reset input terminal of each offlip-flops 501 through 503. The override-set input of each of flip-flops501 through 503 is connected to a fixed voltage of logical value 0.Therefore, each time an X (t) pulse and a C (t) pulse are simultaneouslyapplied to reset AND gate 504, a true pulse is transmitted to theoverride-reset input terminal of each flip-flop to reset, and therebystart, the counter.

Appropriate preset logic determines the number of C (t) pulses thatpositive-tolerance counter 5 will count after being reset. Theresponsiveness of positive-tolerance counter 5 to C (l) pulses dependsupon whether the signal applied to the J and K input terminals offlip-flop 501 has the logical value 1 or 0. The preset logic consists ofan inverter 505, an AND gate 506, and a plurality of switches 507, 508,and 509. The J and K inputs of flipflop 501 are connected to the outputof inverter 505. Inverter 505 is driven by preset AND gate 506. AND gate506 receives one input from each of fiipfiops 501, 502, and 503. Whetherthe 1 or 0 output terminal of a specific flip-flop is connected to ANDgate 506 is determined by the position of the associated single-pole,double-throw switch, viz, switch 507 in the case of flip-flop 501,switch 508 in the case of flip-flop 502, and switch 509 in the case offlip-flop 503. Such switches can be actuated either manually for localadjustment of tolerances or electrically for remote adjustment. Theswitches can also be controlled automatically for adaptive variation oftolerances. The preset logic is so connected that pulses of C (t) arecounted cyclically at all times except when the positive-tolerance countC U) equals the preset value where p; represents the state of switch507+i. As shown in FIGURE 3, p, is 1 when switch 507+i connects the 1output terminal of flip-flop 501+i to AND gate 506 and is 0 when switch507+i connects the 0 output terminal of flip-flop 501+i to AND gate 506.Consequently, once positive-tolerance counter 5 has been reset so that C(t) is 0, the enabling inputs J and K of fiip-fiop 501 are held trueuntil p pulses of C (t) have been counted. The count C U) then equals pand counting stops. For the case illustrated in FIGURE 3 where p=2(binary 010), switch 507 is positioned to transmit the 0 output offlipflop 501, switch 508 to transmit the 1 output of flip-flop 502, andswitch 509 to transmit the 0 output of flip-flop 503.

The normally false output, Xp(t), of positive-tolerance counter 5 isobtained from the output of inverter 505. Each time positive-tolerancecounter 5 is reset, a pulse of length (p /2)'r+'r starting at time t +1-is emitted, where i is a positive integer.

Negative-tolerance counter 6 operates in a maner similar to that ofpositive-tolerance counter 5 except for the enabling inputs X 0) and X0) applied to reset AND gate 604. Negative-tolerance counter 6 can bereset only when these two enabling signals are simultaneously true,i.e., when C (t)X (t)X (t)X (t)=1.

Pulses of C (t) are counted cyclically by negative-tolerance counter 6at all times except when the negativetolerance count C (t) equals thepreset value.

where w is the number of stages in negative-tolerance counter 6 and q,represents the state of switch 607 +i. For the case illustrated inFIGURE 3 where q=1 (binary 001), switch 607 is positioned to transmitthe 1 output of flip-flop 601, switch 608 to transmit the 0 output offlip-flop 602, and switch 609 to transmit the 0 output of fiip-flOp 603.

The output signal X (t) is normally false. Each time negative-tolerancecounter 6 is enabled by an )(,,,,(t) pulse, however, a pulse of length(q /2)r+1- starting at time tsbk T is emitted.

Otherwise, the operation of negative-tolerance counter 6 is the same asthat just described for positive-tolerance counter 5 and can be derivedfrom the preceding description by substituting X (t) for X,,,(t), bysubstituting X U) for Xp(t), and by adding to the number designatingeach inverter, flip-flop, AND gate, and switch to which reference wasmade in discussing positive-tolerance counter 5.

Waveforms relating to positive-tolerance counter 5 are shown in FIGURE 4for the case where p=2 (binary 010). More particularly, waveform 18shows the output of reset AND gate 504, waveforms 19, 20, and 21 showthe outputs of flip-flops 501, 502, and 503, respectively, and waveform22 shows the output X (t) of positivetolerance counter 5.

In accordance with Relation (40), the states of flipflops 501, 502, and503 initially indicate that positivetolerance counter 5 has stopped atthe preset value C U) =p =2 (binary 010). When the true X ,,(t) pulse at30 enables reset AND gate 504, however, the C (t) pulse at 28 istransmitted by AND gate 504 at 47 to reset any flip-flop not already inthe false state, thereby starting the counter at C (t) (binary 000).Consequently, flip-flop 502 goes false at 48.

The signal X (t) goes true at 49' because at least one input signal ofpreset AND gate 506 now has the logical value 0. Since preset switches507, 508, and 509 have been set in accordance with Relation (41) torepresent the number p=2 (binary 010), X (t) will remain true untilflip-flops 501 and 503 are false and flip-flop 502 is true. Because X(t) is used to enable the lowest-order flip-flop, 501, however, C (t)pulses will be counted as long as the X (t) pulse at 50 remains true.

Flip-flop 501 responds to the C (t) pulse at 51 by going true at 53,flip-flops 502 and 503 remaining false to yield a count C (t)=1 (binary001). The next C (t) pulse, at 52, initiates a 1-to-0 transition at the1 output terminal of flip-flop 501, which causes flip-flop 502 to gotrue. The positivetolerance count C U) is then 2 (binary 010).

For the first time since flip-flop 502 went false at 48, all inputs tothe preset AND gate 506 are now true. Consequently, AND gate 506transmits a true output to inverter 505, the output X (t) of whichresponds by going false at 55, thereby stopping the counter untilanother X ,,(t) pulse appears. In this manner, at a time T before itstermination, each X ,,(t) pulse initiates the required X (t) pulse ofduration (p /2)'r+r Thus, the succeeding X (t) pulses at 33 and 34 causethe X U) pulses at 56 and 57, respectively, to be generated. The outputof flipflop 503 remains false continuously at 58 because a value of pless than 4 (binary 100) was chosen for illustration.

The normally false output X (t) of negative-tolerance counter 5 is shownas waveform 23 in FIGURE 4 for the case where q=1 (binary 001). For allvalues of 1 shown in FIGURE 4, the enabling signals X (t) and X 0) aresimultaneously true in accordance with Relation (4). At a time vbeforeits termination, each of the X,,-,,(z) pulses at 44, 45, and 46,respectively, initiates a corresponding X (t) pulse of length (q-/2)'r+'r shown at 59, 60, and 61.

As shown in FIGURE 3, the outputs of positive-tolerance counter 5 andnegative-tolerance counter 6 are applied to the inputs of pass gate 7.Pass gate 7 generates an output pulse whenever an error measurementpasses the test defined by Relation (12). If both X,,(t) and X (t) areasynchronous and statistically independent of C (t), as in the caseillustrated in FIGURE 4, it is then assumed that the error measuredsatisfies Relation (18). If X (t) is synchronized by l-to-O transitionsof C 0), the error measured satisfies Relation (5).

Pass gate 7 consists of a single component, AND gate 701, whichreceives, as its inputs, X (t) from positivetolerance counter 5 and X(t) from negative-tolerance counter 6. When both X (t) and X (t) aresimultaneously true, AND gate 701 functions to indicate by a true pulseat X (t) that adjacent 0-to-1 transitions of X (t) and X (t) satisfyRelation (12). AND gate 701 identifies this condition from simultaneousoccurrence of the conditions Xp(l)=1 and X (t)=1 at its inputs. Theoutput X (t) of AND gate 701 also constitutes the output of pass gate 7and of the wave-edge comparator.

The normally false output of pass gate 7 is shown as waveform 24 inFIGURE 4. This signal goes true only during those intervals when X (t),shown as waveform 22, and X (t), shown as waveform 23, aresimultaneously true. Thus, the X (t) and X U) pulses at 50 and 59,respectively, overlap to generate the X (t) pulse at 62. Similarly, theX (t) and X (t) pulses at 56 and 60, respectively, overlap to generatethe X (t) pulse at 63. Because the X (t) and X (t) pulses at 5'7 and 61,respectively, do not overlap, they do not initiate an X (t) pulse.

Although the positive transitions of X,,(t) and X (t) at 25 and 41,respectively, coincide, the positive transitions of X,,(t) at 31 and 32progressively lead those of X (t) at 42 and 43, respectively. The X (t)pulses at 62 and 63 indicate that the sets of X (t) and X (t)transitions at 25 and 41 and at 31 and 42 have initiated sets of X (t)and X (t) pulses at 30 and 44 and at 33 and 45 which satisfy Relation(12). Conversely, since no corresponding X (t) pulse results, thecomparator indicates that the set of X (t) and X (t) pulses at 32 and 43has generated a set of X (t) and X (t) pulses at 34 and 46 which failsto satisfy Relation (12).

It is, therefore, seen that there is provided, in accordance with thepresent invention, a wave-edge comparator which is operative toindicate, by digital means and on a go or no-go basis, whether or notthe time displacement between corresponding transitions of two logicalsignals is within predetermined tolerances. Either or both of thesignals can be asynchronous. The bilateral tolerances utilized can beunequal and can be remotely adapted to meet time-varying operatingconditions.

The comparator of the present invention provides several uniqueadvantages. A discrete output is produced which requires no furtherinterpretation. In addition to being bilateral, the tolerances utilizedcan be unequal. All components are standard digital types, makingmicrominiaturization straightforward and leading to high operationalreliability. The output of the comparator is fully compatible with theinput requirements of typical on-line computational equipment.

While the invention has been described with respect to the preferredphysical embodiment constructed in accordance therewith, it will beapparent to those skilled in the art that various modifications andimprovements may be made without departing from the scope and spirit ofthe invention.

I claim:

1. Means responsive to signals received in first and second channels,said means comprising: a source of clock pulses; means for determiningwhether a signal in said first channel occurs within a first selectabletime, as a function of said clock pulses, after a signal in said secondchannel;

means for determining whether a signal in said second channel occurswithin a second selectable time, as a function of said clock pulses,after a signal in said first channel.

2. The combination of claim 1 wherein said first and second selectabletimes are independently selectable as a function of said clock signal.

3. In combination: means responsive to a first input signal forgenerating a third signal having a selectable time duration;

means responsive to a second input signal for generating a fourth signalhaving a time duration which is independently selectable from said firsttime duration; and

means for determining coincidence between said third and fourth signals;

a source of clock pulses; and wherein said means for generating a thirdsignal comprises:

first preset counting means responsive to said first input signal forcounting said clock pulses until a first predetermined count is reachedand for generating a first pulse whose duration is proportional to saidfirst predetermined count; and wherein said means for generating afourth signal comprises:

second preset counting means responsive to said second input signal forcounting said clock pulses until a second predetermined count is reachedand for generating a second pulse whose duration is proportional to saidsecond predetermined count.

4. The combination of claim 3 wherein said means for determiningcoincidence comprises:

gate means responsive to said first and second pulses for generating anoutput pulse upon the simultaneous occurrence of said first and secondpulses.

5. The combination of claim 3 wherein said first and secondpredetermined counts are independently selectable.

6. In combination:

means for generating a first signal upon the occurrence of a first eventand a second signal upon the occurrence of a second event; and

means responsive to said first and second signals for generating anoutput signal when the time displacement between said first and secondsignals lies within prescribed bilateral tolerances;

said means for generating first and second signals comprises:

a first step detector responsive to a signal indicating the occurrenceof said first event for generating a first pulse of predeterminedduration a predetermined time after the occurrence of said first eventindicating signal; and

a second step detector responsive to a signal indicating the occurrenceof said second event for generating a second pulse of predeterminedduration a predetermined time after the occurrence of said second eventindicating signal.

7. The combination of claim 6 wherein said means for generating anoutput signal comprises:

a positive-tolerance counter responsive to said first pulse forgenerating a third pulse the duration of which is adjustable to set thepermissible time displacement between said first and second signals whensaid first signal occurs first in time;

a negative-tolerance counter responsive to said second pulse forgenerating a fourth pulse the duration of which is adjustable to set thepermissible time displacement between said first and second signals whensaid second signal occurs first in time; and

gate means responsive to said third and fourth pulses for generatingsaid output signal upon the simultaneous occurrence of said third andfourth pulses.

8. The combination of claim 7 further comprising:

a source of clock pulses, said clock pulses being applied to said firstand second step detectors and said positiveand negative-tolerancecounters for synchronizing the leading and trailing edges of said first,second, third and fourth pulses.

9. The combination of claim 7 further comprising:

a source of clock pulses; and wherein said positivetolerance countercomprises:

first preset counting means responsive to said first pulse for countingsaid clock pulses until a first predetermined count is reached and forgenerating said third pulse whose duration is proportional to said firstpredetermined count; and wherein said negativetolerance countercomprises:

second preset counting means responsive to said second pulse forcounting said clock pulses until a second predetermined count is reachedand for generating said fourth pulse whose duration is proportional tosaid second predetermined count.

10. The combination of claim 9 wherein said first and secondpredetermined counts are independently adjustable.

References Cited UNITED STATES PATENTS 2,861,184 11/1958 Alexander etal. 328109 X 2,866,092 12/1953 Raynsford -328109 X 3,138,759 6/1964Thompson 328l09 X 3,139,539 6/1964 Hewett 307-234 3,209,265 9/1965 Bakeret al 328l09 X 3,268,743 8/1966 Noumey 328-109 X MALCOLM A. MORRISON,Primary Examiner C. E. ATKINSON, Assistant Examiner US. Cl. X.R. 307232;328109

